Job Description
Tenstorrent is seeking an RTL Design Engineer to join their AI core design and verification team. The engineer will be responsible for architecting, developing, and verifying the Tensix core, which supports modern AI workloads. This role is hybrid, based out of Santa Clara, Austin, or Toronto.
Responsibilities:
- Design and implement scalable RTL analysis methodologies.
- Integrate EDA tools and scripts for automation of RTL analysis workflows.
- Conduct analysis of RTL code to optimize design metrics.
- Collaborate with RTL design and emulation teams to define and implement best practices.
Requirements:
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- 5+ years of experience with ASIC design, tools, and methodologies.
- Hands-on expertise with RTL linting EDA tools.
- Proficient in hardware description languages (Verilog, SystemVerilog).
- Skilled in scripting languages (Tcl, Python).
- Strong debugging and problem-solving abilities.
- Excellent communication skills.
Tenstorrent offers:
- A highly competitive compensation package and benefits.