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Job Description
Tenstorrent is seeking a Chiplet Physical Design Engineer to join their team in Japan. This role involves working on a high-profile project focused on designing and integrating multiple chiplets into a System-in-package, collaborating with external stakeholders and Tenstorrent's global experts. The engineer will be responsible for synthesis and place and route for high-speed CPU core design using industry-standard tools. Knowledge of cutting-edge silicon technology (5nm and lower) and multi-GHz design is a plus.
Responsibilities:
- Synthesis and Place and Route using industry standard tools for high speed CPU core design
- Plan out resources, schedule, project PPA
- Develop strategies to deliver reproducible design convergence results
- Help to create and refine synthesis and PNR flow for the project team
- Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure
- Develop and recommend better design methodologies to enable better timing convergence
- Guide and mentor junior engineers
- PV convergence (including static timing and power analysis)
- Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
- Scripting in an interpreted language, minimum TCL in addition to at least one other
Requirements:
- Advanced degree in electrical, computer engineering or computer science
- Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
- Experience with PV convergence, including static timing and power analysis
- Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks
- Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
- Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs
- Expertise in timing closure and block/chip levels and ECO flows
- Experience with scripting in an interpreted language (Python, TCL)
- Willingness to work with others in a highly complex decision space
- Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule
- Excellent verbal and written communication in English, and collaboration skills
Tenstorrent offers:
- Highly competitive compensation package and benefits
