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Job Description
Tenstorrent is seeking a Sr. Staff RTL Core Engineer to join their team in Santa Clara, CA. This role involves working on high-performance silicon and collaborating with a highly experienced team to deliver a functional, timing, and power-converged block. The ideal candidate will be responsible for RTL design and microarchitecture of interconnect and related subsystems, working closely with DV and PD teams.
Responsibilities:
- RTL design and Microarchitecture of interconnect and related subsystems, working closely with the DV and PD teams
- Work with IP vendors, verification, test and post silicon validation teams for high quality design delivery.
- Deploy innovative techniques to improve power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
- Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
- Enhance RTL design environment, tools and infrastructure
Requirements:
- BS/MS/PhD in EE/ECE/CE/CS with at least 6 years of industry experience
- Experience with high performance interfaces (PCI, UCIe, ethernet)
- Experience with SoC design aspects including integration
- Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
- Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
- Expertise in microarchitecture definition and specification development
- Strong problem solving and debug skills across various levels of design hierarchies
Tenstorrent offers:
- A highly competitive compensation package and benefits
