Staff, Design for Test Engineer (DFT)

Job Description

Tenstorrent is seeking a Staff Design for Test (DFT) Engineer to join their team in Bengaluru, India. The successful candidate will play a crucial role in the implementation of DFT features for high-performance designs used in industry-leading AI/ML architectures. This hybrid role offers the opportunity to work collaboratively with experienced engineers across various ASIC domains, contributing to all implementation aspects from RTL to tapeout for various IPs on the chip.

Responsibilities:

• Implementation of DFT features into RTL using Verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry-standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate-level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front-end and physical design flows.

Requirements:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry-standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem-solving and debug skills across various levels of design hierarchies.

Tenstorrent offers a highly competitive compensation package and benefits.