CPU/AI/SOC Physical Design Lead

Job Description

Tenstorrent is seeking a Physical Design Lead to contribute to cutting-edge AI technology. The candidate will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip, working alongside experienced engineers. This is a hybrid role based in Santa Clara, CA, Austin, TX, or Ft. Collins, CO.

• Define PD requirements
• Perform physical design tasks including synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning, and power optimization
• Engage in discussions with 3rd party IP providers, foundry partners, and design services
• Handle end-to-end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance, and area of the design

• BS/MS/PhD in EE/ECE/CE/CS
• Minimum BS and 10+ years of experience in Physical Design
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

• Competitive compensation package and benefits