SOC Physical Verification Lead

Job Description

Tenstorrent is seeking a SOC Physical Verification Lead to manage physical verification for high-performance designs. The candidate will be responsible for full chip and sub-block floor planning, providing collaterals for block-level physical implementation, and top-level SoC integration. They will collaborate with Architecture, RTL, and packaging teams to drive decisions and ensure layout verification closure. The ideal candidate will drive and own top-level SoC floorplan methodology and tools.

Responsibilities include:

• Floor planning of full chip and sub-blocks.
• Top-level SoC integration including RDL, power grid, clocking and bump planning.
• Cross discipline collaboration between Architecture, RTL and packaging teams.
• Driving layout verification closure at SoC level.
• Drive and own top-level SoC floorplan methodology and tools.

Requirements:

• Minimum BS and 10+ years of experience in Physical Design of SoCs.
• Proven track record of successful tape-outs and meeting performance targets.
• In depth practical, hands-on knowledge of the entire P&R methodology.
• Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor.
• Hands-on experience in Power and Signal Integrity analysis.
• Ability to debug and fix LVS, DRC, Antenna, ERC issues.
• Strong communication and teamwork skills.

Tenstorrent offers:

• A highly competitive compensation package and benefits.