RTL Engineer- CPU Load/Store Unit (LSU)

Job Description

Tenstorrent is seeking an RTL Engineer to join their team and work on a high-performance RISC-V CPU. The candidate will collaborate with a team of experienced engineers to deliver a functional, performant, timing and power converged Load/Store unit.Responsibilities:

• RTL design and Microarchitecture of the Load/Store unit
• RTL coding in Verilog
• Work with design, test and post silicon validation teams
• Drive trade-offs for logic
• Deploy innovative techniques for improving power, performance and area
• Debug RTL/logic issues
• Enhance RTL design environment, tools and infrastructure

Requirements:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
• Strong background and experience with high performance OOO CPU microarchitecture
• Experience working on an x86, ARM or RISC-V based CPU
• Architectural understanding of the load/store engines, memory consistency, MMU, Interface protocols for an Out of Order CPU
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
• Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
• Expertise in microarchitecture definition and specification development
• Strong problem solving and debug skills across various levels of design hierarchies

Tenstorrent offers:

• Competitive compensation package and benefits