Staff Design Verification Engineer - CPU Subsystem

Job Description

Tenstorrent is seeking a Staff Design Verification Engineer to join their team in Bangalore, India. The ideal candidate will be responsible for defining verification plans and developing DV environments independently using System Verilog (SV)/UVM. The candidate will create and execute test plans to ensure the quality and reliability of Tenstorrent's IP solutions.

The Staff Design Verification Engineer will play a crucial role in verifying the functionality and performance of Tenstorrent's CPU subsystem.

Responsibilities:

• Define verification plans and develop DV environments independently in System Verilog (SV)/UVM.
• Create and execute test plans to ensure the quality and reliability of our IP solutions.
• Perform functional verification at the RTL level, including coverage analysis and improvement.
• Develop Universal Verification Components (UVCs) from scratch.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• Proven experience in DV and verification methodologies.
• Strong proficiency in System Verilog and UVM.
• Ability to work independently and drive projects to completion.
• Excellent problem-solving and communication skills.

Tenstorrent offers:

• Competitive compensation package and benefits.