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Job Description
Tenstorrent is seeking a STA Lead, Physical Design Engineer to join their team. This role involves working on a high-profile project designing and integrating multiple chiplets into a System-in-package, collaborating with external stakeholders and Tenstorrent's worldwide experts. The candidate will be responsible for STA timing analysis using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus.
Responsibilities:
- Full chip timing analysis from early investigation to final implementation and tape out.
- Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
- Work with architects and logic designers to generate block and full chip timing constraints.
- Analyze scenarios and margin strategies with Synthesis & Design team.
- Partner with physical design teams to close and sign off the designs through PnR and ECO cycles.
Requirements:
- PhD, Masters or Bachelors Degree in EE, EECS or CS.
- Hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC etc.).
- Deep understanding and experience in timing closure of various functional and test modes
- Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, POCV, IR-STA).
- Proficient in scripting (TCL, Perl, Python, csh/bash).
- Problem solver, Efficient written and verbal communication, Excellent organization skills and Mentorship quality.
- Self starter and highly motivated.
- Ability to work cross-functionally with various teams and be productive under aggressive schedules.
Tenstorrent offers:
- Remote work opportunity based out of North America.
- Competitive compensation package and benefits.
