IC Packaging Technologist

Job Description

Astera Labs is seeking an IC Packaging Technologist to drive innovation in high-performance IC package solutions. The candidate will play a crucial role in developing advanced packaging architectures and scaling technologies for high-volume manufacturing.Role involves:

• Leading the development of high-performance, high-speed IC package solutions.
• Innovating in 2.5D/3D packaging and chiplet technology.
• Contributing to strategic roadmap execution.
• Delivering package solutions into production.
• Die-package-board co-design efforts.

Requirements:

• M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.
• 10 years of experience in IC packaging development with deep exposure to SIPI and 2.5D/3D integration technologies.
• Hands-on experience with CoWoS, interposers, WLP, chiplet-based integration.
• Proficiency in SIPI tools: HFSS, Siwave, ADS, HSPICE, etc.
• Expert knowledge of EDA design tools: Cadence Allegro/APD, Altium, etc.
• Experience in high-speed SerDes IC package development.
• Strong background in package SIPI for ultra-high-speed interfaces.
• Extensive engagement with foundries, OSATs, and substrate suppliers.

Role offers:

• Opportunity to work with a global leader in connectivity solutions.
• Chance to contribute to the development of cutting-edge technologies.
• Collaborative environment with cross-functional teams.