Principal Design Verification Engineer - CXL/PCIe

Astera Labs is seeking a Principal Design Verification Engineer to contribute to the functional verification of designs, focusing on PCIe and CXL protocols. The candidate will play a crucial role in developing and executing verification plans, writing test sequences, and ensuring coverage. This role requires collaboration with RTL designers to debug failures and refine verification processes. Astera Labs is a global leader in connectivity solutions, offering a software-defined architecture for AI and cloud infrastructure.

Responsibilities:

• Develop and execute block-level and system-level verification plans.
• Write and execute test sequences and collect and close coverage.
• Collaborate with RTL designers to debug failures and refine verification processes.
• Utilize coding and protocol expertise to contribute to functional verification.
• Develop user-controlled random constraints in transaction-based verification methodologies.
• Write assertions, cover properties, and analyze coverage data.
• Create VIP abstraction layers for sequences to simplify and scale verification deployments.

Requirements:

• Minimum of 8 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
• Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
• Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
• Ability to independently develop test plans and sequences in UVM to generate stimuli.
• Experience writing assertions, cover properties, and analyzing coverage data.
• Developing VIP abstraction layers for sequences to simplify and scale verification deployments.

The role offers:

• Opportunity to work with industry-standard protocols such as PCIe and CXL.
• Chance to collaborate with RTL designers.
• Involvement in developing user-controlled random constraints.