Senior Physical Design Engineer

Job Description

Astera Labs is seeking a Senior Physical Design Engineer to join their team in Bengaluru, India. Astera Labs is a global leader in purpose-built connectivity solutions. This role involves working on complex SoC/silicon products for Server, Storage, and/or Networking applications. The ideal candidate will have a strong academic and technical background in electrical engineering and hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools and methodologies.

• Full chip or block level ownership from architecture to GDSII
• Driving multiple complex designs to production
• Working with IP vendors for both RTL and hard-mac blocks

• Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred
• ≥3 years’ experience supporting or developing complex SoC/silicon products
• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level
• Experience with Cadence and/or Synopsys physical design tools/flows
• Familiarity and working knowledge of System Verilog/Verilog
• Experience with DFT tools and techniques
• Good scripting skills in python or Perl

• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with DFT test coverage and debug
• Familiarity with ECO methodologies and tools