Senior Digital Design Engineering Manager

Job Description

Astera Labs is seeking a Senior Digital Design Engineering Manager to lead the development of high-speed connectivity solutions. This role involves building and managing a team responsible for the micro-architecture and implementation of front-end digital design for high-performance ASICs.About Astera Labs:Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Their Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.Responsibilities:

• Drive the micro-architecture and implementation of front-end digital design.
• Lead a team in RTL design, synthesis, IP integration, and block-level verification.
• Work with high-speed protocols such as CXL/PCIE or Ethernet.

Requirements:

• Strong academic and technical background in electrical engineering (Bachelor’s required, Master’s preferred).
• 15+ years’ experience supporting or developing complex SoC/silicon products.
• 10+ years’ experience managing a team of RTL design engineers.
• Hands-on knowledge of high-speed protocols like CXL/PCIe or Ethernet.
• Proven front end design expertise (architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.).
• Experience with Cadence and/or Synopsys digital design tools/flows.
• Experience with scripting and automation.
• Good knowledge of design for test (DFT).
• Familiarity with UVM based design verification.
• Silicon bring-up and debug expertise.
• Small-geometry CMOS (≤28nm) design.

The role offers:

• The base salary range is USD 247,000.00 USD – USD 260,000.00.