Design Verification (DV) Engineer

Job Description

Hudson River Trading (HRT) is seeking a Design Verification (DV) Engineer to join their Hardware team in London. This team develops high-performance compute engines using FPGA and ASIC technology for low-latency trading. The role involves creating and maintaining testbenches and verification environments for complex HDL designs. The ideal candidate will possess strong testing skills and a desire to improve verification tools and processes.

This person will work to ensure correctness and robustness of HRT's critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities:

• Creating testbenches and tests for our hardware platform
• Writing detailed verification plans
• Root-causing RTL bugs
• Collaborating with designers
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Requirements:

• Superb debug and analytical skills
• 2+ years of professional experience in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

HRT Offers:

• The chance to work with cutting-edge FPGA and ASIC technology
• An innovative and challenging environment
• The opportunity to contribute to open-source projects
• A collaborative and supportive team culture