Design Verification (DV) Engineer

Job Description

Hudson River Trading (HRT) is seeking a Design Verification (DV) Engineer to join its Hardware team in Boulder, Colorado. The team focuses on creating high-performance compute engines using FPGA and ASIC technology for low-latency trading decisions.This role involves creating testbenches and building verification environments for complex HDL. The ideal candidate will be a skilled tester and toolsmith, familiar with the EDA landscape and open-source projects. The role is integral to ensuring the correctness and robustness of critical hardware in a fast-paced environment.Responsibilities:

• Creating testbenches and tests for our hardware platform
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications:

• Superb debug and analytical skills
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

HRT offers:

• The estimated base salary range for this position is $175,000 to $225,000 per year
• Discretionary performance-based bonuses
• Competitive benefits package