Design Verification (DV) Engineer

Job Description

Hudson River Trading (HRT) is seeking a skilled Design Verification (DV) Engineer to join their Hardware team in Austin, TX. The team builds high-performance compute engines using FPGA and ASIC technology for low-latency trading. The candidate will develop and maintain verification environments for complex HDL.

The Design Verification Engineer will work on:

• Creating testbenches and tests for our hardware platform
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

The ideal candidate should have:

• Superb debug and analytical skills
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

HRT offers:

• A scientific approach to trading financial products
• A sophisticated computing environments for research and development