Design Verification (DV) Engineer

Job Description

Hudson River Trading is seeking a Design Verification (DV) Engineer to join its Hardware team in New York. The company builds high-performance compute engines using FPGA and ASIC technology for low-latency trading. The engineer will be responsible for creating testbenches and building verification environments to exercise complex HDL.

The role involves:

• Creating testbenches and tests for hardware platforms.
• Writing detailed verification plans.
• Root-causing RTL bugs.
• Collaborating with designers.
• Managing test suites and continuous integration infrastructure.
• Developing and improving open-source and internal tools.

Requirements include:

• 2+ years of experience in RTL functional verification for FPGA or ASIC.
• Experience with code and functional coverage collection/analysis.
• Experience with SystemVerilog and industry-standard frameworks such as UVM.
• Comfortable in a Linux environment.
• Familiarity with Verilator and/or Cocotb (preferred).
• C++ experience is a plus.
• A bachelor’s degree in computer science, electrical engineering, or a related field.

Hudson River Trading offers:

• The estimated base salary range for this position is $175,000 - $225,000 per year
• Discretionary performance-based bonuses
• A competitive benefits package