Design Verification (DV) Engineer

Job Description

Hudson River Trading (HRT) is seeking a Design Verification (DV) Engineer to join their Hardware team in Chicago. The team builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions. The DV Engineer will be responsible for creating testbenches and building verification environments to ensure the correctness and robustness of critical hardware in a fast-paced, real-time environment.

No financial experience is necessary for this role.

Responsibilities:

• Creating testbenches and tests for our hardware platform
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications:

• Superb debug and analytical skills
• 2+ years of experience in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

What HRT offers:

• The estimated base salary range for this position is $175,000 to $225,000 per year
• Eligible for discretionary performance-based bonuses and a competitive benefits package