Principal Digital Design Engineer-SOC

Job Description

Astera Labs is seeking a Principal Digital Design Engineer to contribute to the development of advanced connectivity solutions. This role involves designing and implementing high-performance digital solutions, with a focus on RTL development and synthesis. The engineer will collaborate with cross-functional teams on IP integration for processor IPs and peripherals.Role responsibilities:

• Designing and implementing high-performance digital solutions, including RTL development and synthesis.
• Collaborating with cross-functional teams on IP integration for processor IPS and peripherals.
• Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
• Owning block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensuring timing closure, assessing verification completeness, and overseeing pre- and post-silicon debug.
• Utilizing tools from Synopsys/Cadence and apply expertise in UVM-based verification flows.

Requirements:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 12+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.
• Hands-on experience with processor IP (ARM/ARC).
• Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
• Hands-on experience with complex DMA engines and FW interaction
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Silicon bring-up and post-silicon debug experience.
• Familiarity with Synopsys/Cadence tools and UVM-based design verification.

Preferred:

• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus
• Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development.
• Familiarity with working in design and verification workflows in a CI/CD environment.