Senior Design Verification Engineer - CXL/PCIe

Job Description

Astera Labs is seeking a Senior Design Verification Engineer to contribute to the functional verification of designs, specializing in PCIe and CXL protocols. The engineer will develop and execute verification plans, write test sequences, and collaborate with RTL designers to debug failures and refine verification processes.

Responsibilities:

• Develop and execute block-level and system-level verification plans.
• Write and execute test sequences, and collect and close coverage.
• Collaborate with RTL designers to debug failures and refine verification processes.
• Utilize coding and protocol expertise to contribute to functional verification.
• Develop user-controlled random constraints in transaction-based verification methodologies.
• Write assertions, cover properties, and analyze coverage data.
• Create VIP abstraction layers for sequences to simplify and scale verification deployments.

Requirements:

• Minimum of 5 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
• Strong academic and technical background in Electrical Engineering or Computer Engineering (Bachelor’s degree required, Master’s preferred).
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Experience in interpreting PCIe/CXL standard protocol specifications.
• Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
• Ability to independently develop test plans and sequences in UVM to generate stimuli.

Astera Labs offers:

• Opportunity to work on cutting edge PCIe and CXL protocols.