Senior Digital Design Engineer-CXL/PCIe

Job Description

Astera Labs is looking for a Senior Digital Design Engineer. In this role, the engineer will design and implement high-performance digital solutions, including RTL development and synthesis. The engineer will be responsible for collaborating with cross-functional teams on IP integration for PCIe/CXL protocols, ensuring timing closure, and assessing verification completeness. The ideal candidate will utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows.Role Involves:

• Designing and implementing high-performance digital solutions.
• Collaborating on IP integration for PCIe/CXL protocols.
• Ensuring timing closure.
• Assessing verification completeness.

Requirements:

• Bachelor's in Electrical Engineering (Master's preferred).
• 7+ years of digital design experience.
• 2+ years focused on high-speed PCIe/CXL implementation.
• Expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Silicon bring-up and post-silicon debug experience.
• Familiarity with Synopsys/Cadence tools and UVM-based design verification.

Role Offers:

• Opportunity to work with high-speed protocols like PCIe/CXL (Gen4+).
• Chance to contribute to cutting-edge connectivity solutions.
• Exposure to advanced nodes (≤ 16nm) design.
• Experience in a CI/CD environment.