Senior Digital Design Engineer - SOC

Job Description

Astera Labs is seeking a Senior Digital Design Engineer to contribute to the development of advanced connectivity solutions. The engineer will be based in Bengaluru, India, and will be involved in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration.

The role includes ownership of block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. The Senior Digital Design Engineer will ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug, utilizing tools from Synopsys/Cadence and applying their expertise in UVM-based verification flows.

Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for processor IPS and peripherals
• Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
• Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows

Requirements:

• Bachelor's in Electronics /Electrical Engineering (Master's preferred).
• 5+ years of digital design experience, with 3+ years focused on processor, peripherals and full chip implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.
• Hands-on experience with processor IP (ARM/ARC)
• Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Silicon bring-up and post-silicon debug experience.
• Familiarity with Synopsys/Cadence tools and UVM-based design verification.

The role offers:

• Opportunity to work on cutting-edge connectivity solutions.