Principal Analog Mixed-Signal IC Layout Engineer

Job Description

Astera Labs is seeking a Principal Analog Mixed-Signal IC Layout Engineer. The candidate will contribute to designing advanced CMOS products. The role involves floor planning, creating layout of building blocks, and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. The focus will be on minimizing parasitic and skew, matching, EMIR, and antenna rule on top of DRC and LVS. The company values teamwork and seeks a motivated individual to collaborate with layout and design engineers across multiple time zones.

• Floor planning
• Creating layout of building blocks
• Integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes
• Minimizing parasitic and skew
• Matching
• EMIR
• Antenna rule on top of DRC and LVS

• Bachelor or advanced Diploma degree in EE
• 5+ years of experience developing layout for highspeed analog IC designs in finFET technology
• Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for highspeed circuits
• EMIR and antenna DRC rules aware layout practices
• Experience writing SKILL and TCL scripts is highly recommended