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Job Description

Astera Labs is seeking a Principal Design Verification Engineer to contribute to their connectivity solutions for AI and cloud infrastructure. The candidate will be responsible for verification aspects using UVM and C/C++.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.

Responsibilities

  • Integrate C/C++ in System Verilog environments using DPI/PLI.
  • Develop infrastructure and tests in hybrid directed and constrained random environments.
  • Develop test-plans and test-sequences in UVM to generate stimuli and debug failures.
  • Write assertions, cover properties, and analyze coverage data.
  • Develop VIP abstraction layers to simplify and scale verification deployments.

Requirements

  • Strong academic and technical background in electrical engineering (Bachelor’s required, Master’s preferred).
  • 8+ years’ experience developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Experience with integrating C/C++ in System Verilog environments using DPI/PLI
  • Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
  • Experience in developing infrastructure and tests in a hybrid directed and constrained random environments
  • Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
  • Develop user-controlled random constraints in transaction-based verification methodology.
  • Experience writing assertions, cover properties and analyzing coverage data
  • Must have prior experience using Verification IPs from 3rd party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
  • Develop VIP abstraction layers to simplify and scale verification deployments

The role offers

  • Opportunity to work on cutting-edge connectivity solutions for AI and cloud infrastructure.
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