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Job Description
Claros Inc., located in Torrance, CA, is seeking a Senior Principal Analog Power Management Integrated Circuit (PMIC) Design Engineer (Technical Lead) to join their ASIC team. This role involves designing and developing high-performance analog circuits for PMICs, collaborating with other engineers, and leading a group of designers in implementing commercial products. The candidate will report to the VP of Engineering and contribute to the evolution of Analog/Mixed-Signal (AMS) circuits.
Role Involves:
- Designing and developing high-performance analog circuits for PMICs.
- Collaborating with engineers to define design methodologies.
- Planning and leading a group of designers.
- Working with multi-disciplinary teams.
- Summarizing and interpreting performance check results.
- Supervising layout circuit designers.
- Behavior and transistor level circuit design.
- Working with PCB layout engineers.
- Datasheet drafting and reviews.
- Working with product managers to develop new products.
Requirements:
- Bachelor’s degree in electrical engineering with 8+ years of experience.
- Knowledge of semiconductor manufacturing processes.
- Experience in High voltage (BCD) and FinFET technology.
- Strong background in Power Management devices and circuit design.
- Released at least one full IC design to production.
- Good knowledge in device physics and reliability analysis.
- Proficiency in Cadence IC Design Tools.
- Familiarity with industry standard interface protocols.
- Ability to document design techniques.
- Strong analytical and problem-solving skills.
- Excellent communication and collaboration skills.
What Claros Offers:
- Career track opportunity with potential for rapid advancement.
- 100% employer paid, comprehensive health care.
- Paid maternity and paternity leave.
- Unlimited PTO.
- Opportunities for professional development.
- Optional 401K, FSA, and equity incentives.
